As use of and demand for semiconductor devices increases, improvements in size, performance and yield are constantly being developed and improved. Achieving the objectives of miniaturization and higher packing densities continue to drive the semiconductor manufacturing industry toward improving semiconductor processing in every aspect of the fabrication process. Semiconductor manufacturers often employ metrology techniques to improve the quality of the wafers and the wafer manufacturing processes. For example, semiconductor metrology information is utilized to calibrate device simulators, aid in electrical testing, predict the performance of devices during the manufacturing process, aid in semiconductor research and development, or aid in process control for present or future semiconductor manufacturing techniques. In addition, metrology is used to aide in feedback or feed-forward semiconductor manufacturing.
Semiconductor fabrication is a manufacturing process that includes a large number of steps and/or processes that control and build the devices. The basic processes utilized are layering, doping, heat-treating, and pattering. The layering process adds thin layers to a wafer surface. Layers can be insulators, semiconductors and/or conductors, for example, and are grown or deposited through a variety of process including chemical vapor deposition (CVD), evaporation, and sputtering. The doping process adds specific amounts of dopants to the wafer surface, which can modify the layer properties (e.g., change a semiconductor to a conductor). Doping techniques include thermal diffusion and ion implantation. During the heat-treating process, a wafer is heated and cooled to achieve specific results.
The various processes involved in creating a semiconductor wafer all exhibit variations that are not always accurately predicted using current design methods. These variations may result from approximations made during the design process, material heterogeneity, containments introduced during the manufacturing process, limitations in manufacturing accuracy or precision, or from unknown sources. It is thus advantageous for a manufacturer to assess the physical characteristics of a wafer throughout and after the manufacturing process to improve performance and yield of the wafer. Measurements made during the manufacturing process may be used to determine the shape metrology of the components on the wafer to help achieve the manufacturer's goals.
Transistor gate metrology (e.g., size, shape . . . ) is especially useful for wafer analysis and several methods are employed to determine the dimensions of the transistors on a wafer. Certain metrology techniques are used to measure the thickness of various layers found on a wafer or transistor including measurement of film thickness of the dielectric layers or film thickness of the gate layers. Image processing from, a critical dimension scanning electron microscope (CD-SEM) is also used to determine shapes of the various structures including the top-down shape of the gates. Overlay data is also used to determine which part of the gate feature actually falls within the source/drain implant region to form the active transistor.
However, none of these metrology techniques can provide a complete picture for a transistor gate, because the measurements taken typically only produce accurate two-dimensional views. In contrast, an accurate, three-dimensional view of a transistor gate would be much more beneficial in connection with numerous areas of the semiconductor manufacturing process.